1. Technical Field
This disclosure relates to a technology of a delay time generation circuit for use in delaying a signal of an electronic circuit and, in particular, to a delay time generation circuit capable of reducing a delay time at testing an electronic circuit, a semiconductor device for protecting secondary batteries using the delay time generation circuit, a battery pack, and an electronic device.
2. Description of the Related Art
Easy-to-use battery packs have widely been used as power sources for various portable electronic devices. The battery packs are formed into a package storing one or plural secondary batteries, and high capacity ones such as lithium-ion batteries, lithium polymer batteries, and nickel hydride batteries are used as the secondary batteries. As the high capacity secondary batteries hold an extremely large amount of energy, they generate heat at high temperature and may sometimes cause ignition in cases of an overcharge, an overdischarge, and an overcurrent.
Therefore, a semiconductor device for protecting the secondary batteries from an overcharge, an overdischarge, a charge overcurrent, a discharging overcurrent, and a short-circuit current is installed in the battery pack. When it is necessary to protect the secondary batteries, the semiconductor device for protecting the secondary batteries interrupts a connection between the secondary batteries and a charger or between the secondary batteries and a load device to prevent the generation of heat and the ignition.
The semiconductor device for protecting the secondary batteries has a dedicated detection circuit to detect each of an overcharge, an overdischarge, a charge overcurrent, a discharge overcurrent, and a short-circuit current. Upon detection of an abnormality requiring a protecting operation, the detection circuit outputs an abnormality detection signal and turns off a switch provided between the secondary batteries and the charger (at charging) or between the secondary batteries and the load device (at discharging) to interrupt the connection.
If the switch is turned off immediately after the output of the abnormality detection signal, the power supply to the load device is caused to stop even where the detection signal is output only for a short period of time, for example, by a malfunction due to noise, thereby leading to a problem such as an improper operation of the load device. In order to prevent such an improper operation, the semiconductor device for protecting the secondary batteries is designed in such a manner as to determine as a true abnormality only an abnormality that still continues after a predetermined time has elapsed since the output of the abnormality detection signal, and then to turn off the switch.
The predetermined time is called a delay time. The delay time is different (from several tens of milliseconds to a few seconds) depending on the detected abnormality. In other words, the delay time is set short for a case where the degree of abnormality is large or an urgent case, whereas it is set long for a case where the degree of abnormality is small or a non-urgent case.
For example, the delay times at detecting an overdischarge, an overcurrent, and a short circuit are about 16 ms, 10 ms, and 1 ms, respectively. However, the delay time at detecting an overcharge with an overcharge detection circuit is 1 s or more and may sometimes be about 5 s at a maximum.
If the delay time is waited for in conducting a characteristic inspection, a shipping inspection, or the like for the semiconductor device for protecting the secondary batteries, it will take too much time, thereby causing reduced productivity and increased costs.
The invention disclosed in JP-A-2005-12852 (Patent Document 1) has been made by the present applicant to solve the above problems. According to this invention, the frequency of a clock signal to be supplied to a delay time generation circuit using a frequency counter is increased at testing a semiconductor device to thereby reduce the delay time.
FIG. 1 is a block diagram of the clock signal generation circuit disclosed in the Official Gazette. The circuit is a ring oscillation circuit using inverters 41 through 45. The setting of an oscillation frequency of the ring oscillation circuit makes use of time required for charging and discharging capacitors C1 and C2 with the output of constant current inverters 41 and 44. The oscillation frequency of the ring oscillation circuit can be increased by substantially increasing the constant current value of constant current sources constituting the constant current inverters 41 and 44. Referring to FIG. 1, a description is specifically made below.
In a normal operation, a test signal TEST2 is set to a high level, and PMOS transistors M1 and M2 are turned off. Therefore, since the currents of current sources I3 and I4 are not supplied to the constant current inverters 41 and 44, respectively, the charging and discharging of the capacitors C1 and C2 are performed only by constant current sources I1 and I2, respectively, thereby resulting in long charging and discharging times and a low oscillation frequency.
At the test, the test signal TEST2 is set to a low level, and both of the PMOS transistors M1 and M2 are turned on. Then, since the currents of the current sources I3 and I4 are supplied to the constant current inverters 41 and 44, the charging and discharging of the capacitor C1 and that of the capacitor C2 are performed by the sum current of the current sources I1 and I3 and that of the current sources I2 and I4, respectively, thereby resulting in short charging and discharging times and a high oscillation frequency.
Patent Document 1: JP-A-2005-12852
However, conventional oscillation circuits cannot accurately set the frequency of a clock signal. This is because the current values of the current sources I1 through I4 and the electrostatic capacitances of the capacitors C1 and C2 fluctuate due to the manufacturing tolerance.
In addition, the manufacturing tolerance is found also in the current ratio of the current source I1 to the current source I3 and that of the current source I2 to the current source I4. The more the current ratio is increased, the larger an error in the current ratio becomes. As a result, it is not possible to accurately set the ratio of a low-speed clock frequency in the normal operation to a high-speed clock frequency at the test, and the test time is caused to greatly fluctuate for the semiconductor devices at the test using a high-speed clock.
Moreover, since the ratio of a low-speed clock to a high-speed clock fluctuates, the delay time itself cannot be measured by the high-speed clock.
Besides, the frequency itself of a high-speed clock cannot be greatly increased. This is because, in a case where the frequency of a high-speed clock is increased, there is a need to use an element for a semiconductor device, which operates at high speed. Furthermore, it is necessary to increase the current value of the current sources I3 and I4 for achieving high speed, but an increase in the current value requires a large circuit area for the current source, thereby causing increased size and increased costs for an IC chip.
On the other hand, it will take time to perform the test if the speed of a clock at the test cannot be increased, thereby causing increased inspection costs. Therefore, it is necessary to determine the frequency of the test in consideration of both costs.